The present invention relates generally to integrated circuit design. More particularly, the present invention relates to circuit design techniques to ensure high-speed, low-power operation at reduced supply voltages in semiconductor memory devices.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing supply voltage levels. Previous circuit families operated at 5 volts and 3.3 volts. Current families operate at 1.8 volts and future families will operate at 1.0 volts nominal supply voltage. Under worst case conditions, the supply voltage may be as low as 0.9 volts. These lower supply voltages create design and operation problems.
One problem is encountered when adapting conventional complementary metal-oxide-semiconductor (CMOS) circuits for low voltage operation. Conventional n-channel and p-channel transistors have threshold voltages (also called turn-on voltages) too large for satisfactory operation in low voltage applications. For example, a conventional p-channel transistor has a threshold voltage of approximately xe2x88x921.2 V and a conventional n-channel transistor has a threshold voltage of approximately 1.1 V. In a 1.0 volt supply device, these conventional transistors will never be turned fully on to sink or source current to a load.
One solution is lowering the threshold voltage of the transistors. With the magnitude of the p-channel and n-channel threshold voltages set at, for example, 0.5 volts, the transistors can turn on fully even at worst case supply voltages. This is important to device performance, since the drain current IDS is proportional to the square of the difference between the drain to source voltage VDS and the threshold voltage Vt. However, transistors with low threshold voltages tend to have higher subthreshold current leakage. In a large integrated circuit with thousands or millions of transistors, the total standby current would be too large for practical applications. The large standby current would increase overall power consumption for the device to unacceptable levels.
Accordingly there is a need for an improved method and apparatus for reducing standby current in an integrated circuit, particularly an integrated circuit employing reduced-threshold voltage transistors in a low supply voltage application.
By way of introduction only, an integrated circuit in accordance with the present invention disconnects supply power to the integrated circuit in standby mode to reduce or eliminate standby current. A large transistor is used to supply power to the entire chip. Only the source of the transistor is coupled to the power supply node. A transistor having a relatively low threshold voltage, such as 0.5 volts, is used as the pass transistor. During standby, the gate of this transistor is pumped to a voltage above the supply voltage using a charge pump in order to turn off the transistor fully. The charge pump is driven by a clock circuit which is designed so that there is minimal crowbar current. As a result, the only standby current is in the charge pump and the clock circuit, and both are designed to be minimal. As a result, low threshold voltage devices can be used in a low power supply environment without concern for excessive standby leakage current.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.